Memory Organization of Microcontroller 8051 Family

2.2.1 MEMORY ORGANIZATION
In This post we will discuss the Memory Organization of Microcontroller 8051 Family. Most microprocessors implement a Von Neuman architecture for memory; a shared memory space for data and programs. On the other hand, microcontrollers are used as a central component in control-oriented designs, without a disk drive or a disk operating system. Also, the control program must reside in ROM. For these reasons, the 8051 implements Harvard architecture for its memory; a separate memory space for programs (code) and data, The architecture provides on-chip memory as well as off-chip memory expansion capabilities. The 8051 has three basic memory address spaces:
64K-byte Program Memory
64K-byte External Data Program Memory
256-byte Internal Data Memory
memory organization of 8051
2.2.2 PROGRAM MEMORY ADDRESS SPACE

The 64K-byte Program Memory space consists of an internal and an external memory portion. If the External Access (EA) pin is held high, the 8051 executes out of internal program memory unless the address exceeds 0FFFH. Locations 1000H through FFFFH are then fetched from external program memory. In either case, the 16-bit program counter is the addressing mechanism. Locations 00 through 23H in program memory are used by the interrupt service routines.

2.2.3 DATA MEMORY ADDRESS SPACE memory organization of 8051
The data memory address space consists of an internal and an external memory space. External data memory is accessed when the MOVX instruction is executed.Internal data memory is divided into the following three physically separate and distinct blocks:
Lower 128 bytes of RAM
Upper 128 bytes of RAM (accessible in the 8032/8052 only)
128-byte Special Function Register (SFR) area
The on-chip RAM contains a rich arrangement of general-purpose storage, bit addressable storage, register banks and special function registers. Two notable features are: The registers and input/output ports are memory-mapped and may be accessed like any other memory location. The stack resides within the internal RAM, rather than in the external RAM, as typical of microprocessors. While the upper RAM area and the SFR (Special Function Register) area share the same address locations, they are accessed through different addressing modes. Any location in the general-purpose RAM can be accessed freely using the direct or indirect addressing modes.

2.2.3.1 SPECIAL FUNCTION REGISTERS (SFRS)memory organization of 8051
The 8051 is a flexible microcontroller with a relatively large number of modes of operations. Our program may inspect and/or change the operating mode of the 8051 by manipulating the values of the 8051's Special Function Registers (SFRs). SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal RAM is from address 00h through 7Fh whereas SFR registers exist in the address range of 80h through FFH. Each SFR has an address (80H through FFH) and a name. 8051 has thee types of SFRs. SFRs related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines. Whether a given I/O line is high or low and the value read from the line are controlled by these SFRs.SFRs which in some way control the operation or the configuration of some aspect of the 8051. For example, TCON controls the timers, SCON controls the serial port.The remaining SFRs, are "other SFRs" These SFRs can be thought of as auxillary SFRs in the sense that they don't directly configure the 8051 but obviously the 8051 cannot operate without them. For example, once the serial port has been configured using SCON, the program may read or write to the serial port using the SBUF register.

P0 (PORT 0, ADDRESS 80H, BIT-ADDRESSABLE)
This is input/output port 0. Each bit of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.

SP (STACK POINTER, ADDRESS 81H)

This is the stack pointer of the microcontroller. This SFR indicates where the next value to be taken from the stack will be read from in Internal RAM. If we push a value onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the value 07H, a PUSH instruction will push the value onto the stack at address 08H. This SFR is modified by all instructions, which modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts are provoked by the micro controller.

2.2.3.4 DPL/DPH (DATA POINTER LOW/HIGH, ADDRESSES 82H/83H)
The SFRs DPL and DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding external RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can represent values from 0000H to FFFFH (0 through 65,535 decimal).

2.2.3.5 PCON (POWER CONTROL, ADDRESSES 87H)

The Power Control SFR is used to control the 8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode, which requires much, less power. These modes of operation are controlled through PCON. Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's serial port.


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